Job Title: ASIC Digital Physical Design Engineer Job Description Join a dynamic team where you will execute ASIC digital physical design implementation from RTL or gate-level netlist through GDSII. You will be working on cutting-edge projects, driving place-and-route execution using industry-standard EDA tools, and optimizing designs for timing, power, area, signal integrity, and routability. Responsibilities Execute ASIC digital physical design from RTL or gate-level netlist to GDSII, including floor-planning, placement, clock tree synthesis, routing, and design closure.
Drive place-and-route execution using industry-standard EDA tools, optimizing designs for timing, power, area, signal integrity, and routability. Perform static timing analysis and timing verification across multiple modes and corners, resolving setup, hold, clocking, and constraint-related issues. Support physical signoff activities, including DRC, LVS, formal equivalence checking, extraction, IR drop, electromigration, and signal integrity analysis.
Collaborate with RTL design, verification, DFT, analog, packaging, and product architecture teams to resolve implementation issues and ensure a timing-closed, manufacturable, tapeout-ready design. Develop and maintain scripts, flows, documentation, and review materials to improve physical design methodology, automation, quality, and schedule predictability. Essential Skills BS in Electrical Engineering or equivalent experience.
5+ years of hands-on experience in ASIC physical design from RTL to verified GDS. Hands-on experience with ASIC or SoC physical design implementation, including floorplanning, power planning, place-and-route, clock tree synthesis, routing, and design closure. Experience with static timing analysis, timing constraints, multi-mode multi-corner timing verification, and timing closure at the block or SoC level.
Familiarity with physical signoff checks and related debug activities, including DRC, LVS, extraction, formal equivalence checking, IR drop, electromigration, and crosstalk analysis. Proficiency with industry-standard physical design and timing tools from vendors such as Cadence, Synopsys, or Siemens EDA. Strong scripting and automation skills using Tcl, Python, Perl, or shell scripting. Additional Skills & Qualifications 10+ years of hands-on experience in ASIC physical design from RTL to verified GDS.
MS or PhD in Electrical Engineering or equivalent experience. Principal-level experience leading physical design implementation for complex ASIC or SoC programs. Proven ability to define and drive RTL-to-GDSII physical design strategy, resolve complex tradeoffs, and deliver tapeout-quality results on schedule. Advanced expertise in static timing analysis, timing constraints, multi-mode multi-corner timing verification, clocking methodology, ECO implementation, and timing closure at the SoC, subsystem, and critical-block levels.
Deep experience driving physical signoff readiness and debug. Expert proficiency with industry-standard physical design, timing, extraction, and signoff tools. Demonstrated technical leadership managing internal execution and external ASIC design service providers. Work Environment This is a hybrid role, requiring at least 3 days in the office each week. We provide a collaborative environment where you can work on challenging projects that push the boundaries of technology.
Join us in revolutionizing a better tomorrow. Job Type & Location This is a Contract to Hire position based out of Louisville, CO. Pay and Benefits The pay range for this position is $75.00 - $127.00/hr. Individual compensation offered for this position within this range will depend on many factors, including qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors.
Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change an