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Position: Senior Engineer (Level 1) Job Description: 1. 5 to 8 years of experience in RTL Synthesis, Timing Constraints / SDC checking / reviewing / small fixes / finding errors etc. 2. Should have done at least 3 ASIC projects. 3. CDC, Lint clean up and automation with scripts, TCL, Perl Scripting. 4. Timing Report analysis, Static Timing Analysis 5. Formal Verification familiarity 6. UPF / Low Power Design is a plus.
Tools : 1. Genus / FC : Synthesis, Optimization or DC compiler, DCTopo 2. Spyglass : Constraints checking / CDC Checking 3. LEC / Formality : Formal Verification, VCLP. 4. Primetime : Zero delay Timing analysis. Location: IN-KA-Bangalore, India (eInfochips) Time Type: Full time Job Category: Engineering Services