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SerDes RTL Design Engineer

AMD

San Jose, California
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San Jose, California
Location
AMD
Employer
Ai Engineer jobs
Category

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.

Join us and, together, we’ll advance your career. THE ROLE:   AMD SerDes Technology team is searching for a passionate and innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. THE PERSON:     You have an innovative mindset and a passion for digital design, and verification in general. You are a team player who has excellent communication skills.

You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES:     Collaborate with system link architects to micro-architect cutting edge high-speed SerDes PHY design RTL design of digital blocks, such as calibration and adaptation loops, digital signal processing, clock-data-recovery Apply low power design techniques and perform PPA analysis Verify intended functionality with block-level test bench Run design checker tools such as LINT/CDC/RDC etc.

Behavioral modeling of custom circuit using Verilog/System Verilog Support functional verification and debug of design, and static timing closure Collaborate with physical design and validation teams to perform pre-tape out design sign-off and silicon bring-up PREFERRED EXPERIENCE:     Proficient in logic design concepts and RTL coding using Verilog/System Verilog Proficient in micro-architecture and developing design specifications Proficient with design checker tools and/or functional verification tools Knowledge of synthesis flow and static timing analysis Knowledge of low po

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