Staff SOC DFX RTL Design Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.

Join us and, together, we’ll advance your career. T HE ROLE :   As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: Be a member of the Client SOC DFX team that plays a significant role in ensuring the quality of next generation microprocessors through structured DFX Architecture and edge cutting DFX techniques.

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. K EY RESPONSIBLITIES : DFX Design Planning and Implementation of DFX Features like JTAG, Scan, Boundary Scan, Debug features etc.

Work with CAD, IP team for requirements and implementation and power scenarios. Work with DFX Verification team for Quality. Active involvement in DFX Initiatives and process Development Provide technical support to other cross functional teams Need to be a team player and work Collaboratively with team members P REFERRED EXPERIENCE : Knowledge of DFT techniques such as JTAG/IEEE standards, SSN, Scan and ATPG, memory BIST/repair or Logic BIST Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX   Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design   Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus Hands on experience on DFX implementation, low power technologies.

Experience with latest Scan/MBIST architecture is a benefit Familiarity with Verilog