Digital Accelerator IC Design Trainee Program (all genders)

Welcome to the Fraunhofer Institute for Integrated Circuits IIS! As the largest institute within the Fraunhofer-Gesellschaft, we have been conducting research for over 30 years in diverse fields such as artificial intelligence, microelectronics, sensor systems, data acquisition, signal processing, and signal transmission. Talented individuals from various engineering and natural science disciplines will find a wide range of exciting research topics under one roof.

A few highlights that reflect our innovative strength include neuromorphic computing, 5G/6G mobile communication technologies, generative AI in speech and signal processing, and X-ray imaging for e-mobility. And that’s just the beginning! Are you passionate about microelectronics and ready to launch your career in Digital IC Design? Join our Trainee Program and become part of a growing high-tech ecosystem that’s driving innovation in chip development.

Here's how you will make a difference The program is rooted in the Bavarian Chip Design Center (BCDC), a strategic initiative supported by the Free State of Bavaria. BCDC aims to strengthen the regional semiconductor industry and develop skilled talent in integrated circuit (IC) design. With the increasing demand for chip designers in Europe, especially in Bavaria, there has never been a better time to join this future oriented field.

Introduction to Digital IC Design: You will receive a comprehensive introduction to Digital IC Design under the guidance of experienced engineers and researchers. Practical Design Experience: You will gain hands-on experience in translating system and functional specifications into micro-architectures and implementing digital hardware blocks in RTL. SystemVerilog and RTL Design: You will develop practical skills in SystemVerilog and learn to design key accelerator components such as datapaths, control logic, and memory subsystems.

Accelerator Design and Optimization: You will gain hands-on experience in neural-network accelerator architecture, RTL verification and system integration, while exploring architectural and implementation trade-offs for optimized power, performance, and area (PPA). Research-Oriented Development: You will apply your skills to an integrated accelerator and explore architectural trade-offs and optimization opportunities.

Experience with EDA Tools: You will gain hands-on experience with industry-grade EDA tools. Knowledge of SystemVerilog: You will become familiar with SystemVerilog and learn how to build processor systems and hardware accelerators using the RISC-V architecture. Professional Preparation : You will build a strong foundation for a career in digital IC design and hardware accelerator development. What you bring to the table Master's degree in electrical engineering, computer engineering, computer science, or a related technical field.

Knowledge  of digital systems, computer architecture, programming, and scripting. High level of  motivation  and the ability to  work independently . Strong  team spirit  and good communication skills . A  background in studies  focused on digital hardware, computer architecture, embedded systems, or hardware acceleration is desirable, but not mandatory.

Familiarity  with a hardware description language (HDL) is preferred. Experience  with design tools such as Cadence or Synopsys is considered advantageous. Proficiency in  English  at least at  B2/C1 level . What you can expect Theoretical Experience: You will gain expertise in digital IC and hardware accelerator design, from microarchitecture and RTL to verification and low-power PPA optimization.

Practical Training: We will guide you in translating theoretical concepts into practical hardware designs and developing critical thinking to evaluate real-world design trade-offs. Supportive Environment: We take your goals and needs seriously by providing consistent guidance and support through assigned mentors a