RTL Design & Integration Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.

Join us and, together, we’ll advance your career. THE ROLE As a key member of AMD’s FPGA Product development team, you will have various responsibilities in the technical execution of Adaptive & Embedded Computing Group (AECG) device programs from conception & planning to productization. You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in supporting PPA, cost and schedule optimized Silicon implementation and first-time-right SW solution.

THE PERSON You are passionate about HW architecture, Digital design, and building cutting-edge silicon. As a strong problem solver and analytical thinker, you bring collaboration, communication, and adaptability to cross-functional teams spanning multiple time zones. KEY RESPONSIBILITIES Collaborate with architects, hardware engineers, and SW-FW engineers to understand the product requirements and IP features.

Build early-stage RTL designs based on product and architecture intent driving Silicon and Solution co-development. Build and enhance AI-driven infrastructure to accelerate IP integration and improve development timelines. Apply data-driven methodologies to align engineering teams across next-generation products and technology nodes. Support functional simulation and software quality checks , ensuring robust verification coverage.

Partner with global teams to achieve seamless integration and delivery. PREFERRED EXPERIENCE This is NOT a New/Recent College Grad-level position; Targeting background expertise in RTL design (Verilog/SystemVerilog), including digital/analog block implementation. Understanding of VLSI design flow, from RTL through Physical Design and GDSII. Familiarity with Physical Implementation processes: floorplanning, synthesis, P&R, STA.

Experience with EDA tools (Synopsys Design Compiler, Primetime, VCS; Cadence Virtuoso). Knowledge of UVM/OVM verification, simulation environments, and debugging. Understanding of FPGA architecture and usage models is a plus. Proficiency in scripting (Perl, Tcl, Python, Sh