RTL Design Manager

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.

Join us and, together, we’ll advance your career. T HE ROLE : As an RTL Design Manager for the AECG IP & SOC group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers.

The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Lead a small, high-performance engineering team Own the design and implementation of blocks to meet functional, timing, area and power requirements Guide and review verification for these blocks Design and implement logic functions that enable efficient test and debug Implement automation to increase design team efficiency Strong front-end RTL engineering background Strong communication skills, able to summarize complex problems for executives as well as drill down to details with architects and engineers Strong analytic and problem solving skills including the ability to analyze current behavior, identify potential areas for improvement, and design of experiment P REFERRED EXPERIENCE : Experience with Arm architecture and APB, AXI, CHI protocols Experience with design reuse, including RTL, constraints, and waivers Experience with SoC level design integration Experience with automation using scripting techniques such as PERL, Python, or Tcl Experience with timing constraints and timing exceptions Experience running standard quality checks such as LINT and CDC Experience designing with multiple power domains including writing UPF Must be a self-starter and self-motivated ACADEMIC CREDENTIALS: <li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-