Senior/ IC Design Engineer (Physical Design)

Job Description Perform RTL-to-GDS physical implementation for ASIC IP/subsystem/SoC designs using industry-leading EDA tools and AI-assisted methodologies Develop and execute synthesis, Design-for-Test (DFT), and timing closure strategies, including DRC/LVS, static timing analysis (STA), scan/DFT validation, and GDS tape-out verification, leveraging AI-assisted methodologies to achieve successful tape-out .

Integrate multiple IP blocks and subsystems into a top-level chip layout. Collaborate with cross-functional stakeholders to achieve power, performance, area (PPA), and timing goals. Design, implement, and maintain synthesis, DFT, and STA scripts using industry best practices to improve automation, flow robustness, and design quality. Leverage AI/LLM tools to automate workflows, accelerate analysis, optimize place-and-route (PnR) and timing prediction, and generate design constraints to improve productivity and design quality.

Requirements Bachelor/Master Degree in Electronics/Electrical/Computer Engineering, or a related field, with at least 1 year of relevant experience. Experience in RTL-to-GDS physical design, including synthesis, floor planning, placement, Layout, clock tree synthesis (CTS),routing, timing closure, physical verification, and design optimization. Good understanding of timing constraints development and Static Timing Analysis (STA).

Demonstrated use of LLMs and AI coding assistants to automate workflows, debug scripts, and generate documentation. Proficiency in scripting (Tcl, Python, Perl, Shell, and Makefile), as well as Verilog, SystemVerilog, C, and C++. Experience with AI-assisted backend EDA tools (e.g.,Synopsys, Cadence) is preferred. Self-motivated team player with strong verbal and written communication skills. We invite qualified candidates to submit your CV to [email protected] or apply online.