Job at a glance
Why are We Hiring for this Role: Leading a structured evaluation of technical and business feasibility for a custom inference chip tailored to robotic workloads. Analyzing current bottlenecks in robotic inference pipelines and comparing off-the-shelf vs. custom alternatives. Developing models for performance, cost, scalability, power, and area to inform build-vs-buy decisions. Defining high-level chip architecture optimized for low-latency, real-time systems (e.g., CNNs, transformers, sensor fusion).
Evaluating tradeoffs in dataflow, memory hierarchy, interconnects, and hardware/software interfaces. Guiding RTL prototyping, simulation, and early design exploration. Coordinating with external vendors, foundries, or design houses as needed. Delivering a comprehensive report with recommendations, including technical/financial analysis and risk/benefit tradeoffs. Presenting findings to leadership and, if approved, leading early custom IC design and project planning.
What Kind of Person We Are Looking For: Proven track record in designing or evaluating AI accelerators, neural network inference engines, or signal processing hardware, with a history of delivering end-to-end projects. Deep expertise in hardware/software co-design, embedded compute tradeoffs, and optimizing for real-time, low-power systems. Hands-on experience with RTL design (Verilog/VHDL/SystemVerilog), simulation, synthesis tools, and ASIC/FPGA development.
Ability to model and evaluate AI inference workloads, including performance bottlenecks and architectural tradeoffs. Strong leadership and communication skills to translate complex technical insights into actionable executive recommendations. Experience in robotics, autonomous systems, edge computing, or similar high-stakes environments where scrappiness was key to success. Familiarity with low-power design, mixed-signal integration, hardware security, chip bring-up, verification, and validation.
Prior collaboration with foundries, ASIC vendors, or design houses in resource-constrained settings. M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. 8+ years of experience in digital IC design, SoC architecture, or ASIC/FPGA development, with demonstrated ability to own projects autonomously. Benefits We provide market standard benefits (health, vision, dental, 401k, etc.).
Join us for the culture and the mission, not for the benefits. Salary The annual compensation is expected to be between $210,000.00 - $400,000.00 Exact compensation may vary based on skills, experience, and location.